1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and an operating method thereof, in particular, a nonvolatile semiconductor memory device using a trimming technique and an operating method thereof.
2. Description of the Related Art
In recent years, with miniaturization of the size of a nonvolatile semiconductor memory device, ON-current in a memory cell has been decreased. As the ON-state current is decreased, manufacture variations in a word line voltage and sense amplifier reference current greatly influence on relative relation between the ON-current and the sense amplifier reference current. In such a case, when data in the memory cell is read on the basis of the sense amplifier reference current and the ON-current, the read operation may become unstable.
For the above situation, a trimming scheme (disclosed in, for example, Japanese Laid Open Patent Application (JP-P2004-55081A)) is employed of suppressing the variations in the word line voltage and the sense amplifier reference current in the read operation, in order to properly read data with the reduced ON-current. According to the trimming scheme, first, a wafer test is carried out and then optimum trimming data is determined for each chip of the nonvolatile memory. The determined trimming data is stored in a dedicated memory array area in the nonvolatile memory (hereinafter, referred to as a “trimming data storage area”). Next, in a system initial operation (hereinafter, referred to as a “reset sequence”), the trimming data is read out from the trimming data storage area to set optimum word line voltage and sense amplifier reference current (or reference voltage). Thus, in the subsequent system operation, the read operation can be carried out in the optimum state.
Here, a conventional nonvolatile semiconductor memory device described in Japanese Laid Open Patent Application (JP-P2004-55081A) will be described. FIG. 1 is a block diagram of a conventional nonvolatile semiconductor memory device. The conventional nonvolatile semiconductor memory device has a nonvolatile memory array 101, a plurality of trimming circuits 108 to 111, a decoder circuit 105, a trimming register 106 and a selector circuit 107. Data can be electrically written or erased into or from the nonvolatile memory array 101. The nonvolatile memory array 101 is divided into a user area 102 and a trimming data storage area 103. The user area 102 stores user data therein. The trimming data storage area 103 stores trimming data corresponding to each of operation modes. The plurality of trimming circuits 108 to 111 carries out trimming operations in accordance with each operation mode. The decoder circuit 105 receives a mode signal and designates an address in the nonvolatile memory array 101 in which the trimming data is stored for the operation mode represented by the mode signal. The trimming register 106 stores the trimming data read out from the nonvolatile memory array 101 according to the address designated by the decoder circuit 105. The selector circuit 107 outputs the trimming data held in the trimming register 106 to one of the trimming circuits 108 to 111 corresponding to the operation mode represented by the mode signal.
FIG. 2 is a circuit diagram showing a part of configuration of the nonvolatile memory array 101. The nonvolatile memory array 101 (the user area 102 and the trimming data storage area 103) has a plurality of word lines WL, a plurality of source lines SL, a plurality of bit lines BL, and a plurality of memory cells M. The plurality of memory cells M are nonvolatile memory cells such as flash memory cells. The word lines WL and the source lines SL extend in a first direction and are connected to control gates and sources of corresponding memory cells M, respectively. Each of the bit lines BL extends in a second direction substantially orthogonal to the first direction and is connected to drains of corresponding memory cells M. The memory cells M are provided at intersection points of the word lines WL and the bit lines BL. When a memory cell M11 is selected from the memory cells M, a word line WL3 is selected from the word lines WL, a bit lines BL0 is selected from the bit lines BL and a source line SL1 is selected from the source lines SL.
For example, in FIG. 2, when data is read from the memory cell M11 as the selected cell, a read voltage Vread (word line voltage) is applied to the word line WL3 connected to the control gate of the selected cell M11 and the other word lines WL are set to the ground voltage. A predetermined read voltage is applied to the bit line BL0 connected to the drain of the selected cell M11 and the other bit lines BL are set to the ground voltage. All source lines SL are set to the ground voltage. At this time, data in the memory cell M11 is read by comparing a cell current Ion passing through the memory cell M11 and the bit lines BL with a reference current IREF in a sense amplifier circuit 4.
Next, a read operation of reading out data from the memory cells M of the nonvolatile memory array 101 will be described. Here, for an ON-state memory cell as a selected cell in a first state where a threshold voltage is low (data “0” has been written) and an OFF-state memory cell as a selected cell in a second state where the threshold voltage is high (data “1” has been written), relationship between current and voltage at the read operation will be described. FIG. 3 is a graph showing relationship between the read voltage and cell currents and the sense amplifier reference current. A horizontal axis represents a read voltage Vread (word line voltage) and a vertical axis represents cell current Ion and the sense amplifier reference current IREF. The sense amplifier reference current IREF passes through the sense amplifier (not shown in FIG. 1) in the read operation. The sense amplifier compares the sense amplifier reference current IREF with the cell current Ion to read data. The ON-state memory cell current Ion1 as the cell current Ion passes through the ON-state memory cell. The ON-state memory cell current Ion1 rapidly increases with increase in the word line voltage. On the other hand, The OFF-state memory cell current Ion2 as the cell current Ion passes through the OFF-state memory cell. The OFF-state memory cell current Ion2 increases slightly with increase in the word line voltage. The sense amplifier reference current IREF is set constant irrespective of the word line voltage. The read voltage (word line voltage) Vread applied to the word lines is set to be V0 (for example, 2.5 V). The ON-state memory cell is determined to be in the first state based on the ON-state memory cell current Ion1 larger than the sense amplifier reference current IREF. On the other hand, the OFF-state memory cell is determined to be in the second state based on the OFF-state memory cell current Ion2 smaller than the sense amplifier reference current IREF.
Here, unless both the ON-state memory cell current Ion1 and the OFF-state memory cell current Ion2 have a certain margin with respect to the sense amplifier reference current IREF in case of the read voltage Vread=V0, an operation speed, that is, a read speed of the sense amplifier is decreased. For this reason, the sense amplifier is generally used in the condition that an ON margin ΔIm1 (for example, 5 μA) and an OFF margin ΔIm2 (for example, 5 μA) are ensured. At this time, when there are variations in the word line voltage and the sense amplifier reference current in terms of manufacture yield, since the ON-current (ON-state memory cell current Ion1) is small, influence of the variations is considered to be large. That is, it is expected that the margins (the ON margin ΔIm1 and the OFF margin ΔIm2) cannot sufficiently ensured due to small variations. However, even in this case, since the variations are suppressed by adjusting the word line voltage and the sense amplifier reference current on the basis of the trimming data (TCD, TCD2) to ensure sufficient margins, a proper read operation can be carried out without decreasing the read speed.
However, the trimming data is read out from the trimming data storage area before the word line voltage and the sense amplifier reference current are optimized. In other words, in the read operation of the trimming data from the trimming data storage area 103 during the reset sequence, optimum trimming data cannot be found. For this reason, there is a possibility that the variation in the sense amplifier reference current IREF becomes large. FIG. 4 is a graph showing a relationship between the read voltage, the cell currents and the sense amplifier reference current. A horizontal axis represents the read voltage Vread (word line voltage) and a vertical axis represents the cell current Ion and the sense amplifier reference current IREF. FIG. 4 shows a state that the sense amplifier reference current IREF is shifted relatively greatly due to variation in the sense amplifier reference current IREF (or variation in the ON-state memory cell current Ion1). In case of the read voltage (word line voltage) Vread=V0, the ON margin ΔIm1 between the ON-state memory cell current Ion1 and the sense amplifier reference current IREF becomes about 0 μA and the margin cannot be ensured. This leads a problem that the sense amplifier cannot read correctly data in the ON-state memory cell in the trimming data storage area 103. That is, there is a case where the trimming data cannot be correctly read. Therefore, a method capable of correctly reading the trimming data in the reset sequence before reading the trimming data, even when the ON-state current is small is strongly demanded.